1. Field of the Invention
The present invention relates to a semiconductor memory device and a local input/output division method.
2. Description of Related Art
As a conventional semiconductor memory device, Japanese Unexamined Patent Application No. 2007-87436 discloses a semiconductor memory device which controls switching of routes of latch circuits for external transfer in order to reduce current consumption at a high-speed operation while preventing malfunction at low-speed operation. Also, a conventional synchronous semiconductor memory device disclosed in Japanese Unexamined Patent Application No. 2005-346922 has as its object to provide an SDRAM in which bit constitution can be switched and area penalty is reduced.
Further, a Double Data Rate 3 (DDR3) standard has been proposed for a semiconductor device, such as a Synchronous DRAM (SDRAM), to improve a data read-out speed compared to a 3-mat architecture that is used in a Double Data Rate 2 (DDR2) standard.